The present invention relates to a circuit for controlling the cyclic ratio of a periodic pulse signal, as well as to a device multiplying by 2.sup.n the pulse signal frequency incorporating the said control circuit. This invention is applicable to digital transmission and more particularly to four-state modulation by displacement of phases.
In order to provide a better understanding of the application of the invention, particularly to the four-state modulation by phase displacement, it is useful to point out that in the field of digital transmission, the flow rate of a modulating signal or the data quantity transmitted per second (number of bits per second) is associated with a clock or timing signal H of frequency f.sub.0. The timing signal H is a squarewave signal of cyclic ratio 0.5. The four-state phase modulation results from the composition of two modulations, by two-state phase displacement, for which the frequency of the associated timing signal is equal to f.sub.0 /2 and is then called clock H/2. In a transmission chain with respect to the modulator, the modulating signal is separated into two digital trains A and B, whose flow rates are respectively equal to half the flow rate of the signal to be transmitted. The associated clock H/2 is formed by dividing the frequency of clock H by two, generally using a multivibrator. On reception, after allowing for transmission errors, demodulation supplies digital trains A and B. It also makes it possible to obtain again the clock or timing signal H/2. In order to restore the initial modulating signal by interlacing, it is necessary to restore clock H by doubling the frequency of the timing of clock H/2.
The invention is applied more particularly to the performance of the latter operation, i.e. the transformation of clock H/2 into clock H.
The multiplier device of the invention also includes a circuit for controlling the cyclic ratio of a pulse signal. No simple device is known which makes it possible to rapidly control the cyclic ratio of a periodic pulse signal and also no multiplier is known, which makes it possible to multiply the frequency of a signal by two or by a power n of two, without using numerous, costly means, which are difficult to realize.
Among the devices making it possible to control or regulate the cyclic ratio of a pulse signal, the simplest is formed by a monostable multivibrator, whose conducting period is regulated by selecting appropriate values for the capacitive and resistive elements making it possible to fix the duration of this period. This control is not very precise and it is specific to the frequency of the signal.
The known frequency doublers are of the "analog" type, i.e. of the type with "a phase locking loop."
In an analog doubler, clock signal H/2 of frequency f.sub.0 /2 is applied to the doubler, which provides the double frequency line f.sub.0. It is then necessary to filter the line of frequency f.sub.0 of clock H and then carry out amplification, followed by shape and phase restoration.
In the case of a frequency doubler using a phase locking loop, a voltage-controlled oscillator supplies a signal of frequency f.sub.0, which is double the frequency f.sub.0 /2 of clock H/2. A phase comparison is then performed between the incident signal of frequency f.sub.0 /2 and the signal of f.sub.0 /2 resulting from the division by two of the signal supplied by the voltage-controlled oscillator. The error voltage resulting from this phase comparison makes it possible to lock the voltage-controlled oscillator on frequency f.sub.0 in both frequency and phase. The oscillator output supplies the clock signal H of frequency f.sub.0.
The analog frequency doubler thus comprises a band-pass filter tuned to frequency f.sub.0, a shape restoring amplifier and phase restoring means in order to compensate the time lag caused by filtering. The main disadvantage of this type of doubler is that it is specific to each frequency linked with the digital flow rate. Moreover, the compensation of the range of uncertainties of the frequency of the incident signal is low. Finally, for low speed flows, filtering must be narrow in order to separate the frequency lines, which increases the time lag which has to be compensated.
The frequency doubler of the "phase locking loop" type has better performance characteristics. However, the synchronization and following range of this doubler with respect to the input signal frequency is linked with the factor K.sub.0 of the voltage-controlled oscillator. This factor K.sub.0 is the frequency sweep covered per volt of control voltage applied to the oscillator. In the case of a quartz oscillator, factor K.sub.0 is approximately 10.sup.-3 to 10.sup.-4. Thus, the frequency sweep is very low and this type of double can only be specific to each pulse flow rate to be transmitted. In the case of a conventional oscillator, the flow rate range controlled can vary in a ratio of four between the lowest and highest rates. In order to cover wider ranges, it is necessary to use more complex arrangements requiring range switching operations.